SiNavigator leverages the OA database created by Cadence Design
Systems Inc.
"We chose Synopsys as our verification partner on our latest 90-nanometer,
40-million-gate chip development project after evaluating several providers,"
said Bob Solberg, vice president of Operations and co -founder at SLE. In addition,
Synopsys provides extensive RVM documentation and offers training to enable
both small and large chip development teams to quickly implement industry best
practices for verification.

Synopsys Discovery Verification Platform
The Discovery Verification Platform is a unified environment that provides
high performance and efficiency of interaction among all platform components,
including mixed-HDL simulation, mixed-signal, system-level verification ,
assertions, DesignWare(R) verification intellectual property, code coverage,
functional coverage , testbenches and formal analysis. Synopsys also provides
intellectual property and design services to simplify the design process and
accelerate time-to-market for its customers. Visit Synopsys online at
http://www.
+1-650-584-1644
igamboa@synopsys.

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"The semiconductor industry is moving to the next level of design
productivity by embracing higher levels of abstraction," stated
Devadas Varma, CEO of Calypto. We consider SLEC
an important tool in our high-level design flow .
This can be done while being integrated with Open Access and
leveraging Silicon Navigator engines . Email: info@sinavigator.

synopsys.

subir vlsi

SLEC can verify designs with sequential differences such as
micro-architectural changes, state machine modifications, timing
re-balancing, and interface differences. enables IC design
teams to bridge the system-to-RTL design gap, thereby saving millions
of dollars in design costs and silicon re-spins.com

Library Smart and SiNavigator are trademarks of Silicon Navigator.
Silicon Navigator and Verific Design Automation acknowledge trademarks
or registered trademarks of other organizations for their respective
products and services. Combined with support
for industry-standard hardware design and verification languages, including
Verilog , VHDL, SystemVerilog, SystemC(TM) and OpenVera(R) and Synopsys' proven
Reference Verification Methodology , the Discovery Verification Platform helps
designers achieve higher levels of verification productivity by contributing
to first-time silicon success within required project cycles.

CONTACT:
Isela Warner
Synopsys, Inc.

pepa gueziec

SLEC enables
designers to quickly verify RTL refinements without having to spend
time running a full regression suite.

Silicon Navigator Teams With Verific To Extend OpenAccess Support to Front-End Design; Verific HDL Components Add RTL Capability to SiNavigator Framework

hossein equivalences

J. It develops and sells
C++ source code-based SystemVerilog, Verilog and VHDL front ends --
parsers, analyzers and elaborators -- as well as a generic
hierarchical netlist database for EDA applications.
(Nasdaq: SNPS), a world leader in semiconductor design software, today
announced that Silicon Logic Engineering (SLE), a provider of high-end ASIC
and system design services, has adopted Synopsys' VCS (R) comprehensive RTL
verification solution and Vera(R) testbench automation tool to accelerate its
chip development process. The company delivers technology-leading
semiconductor design and verification platforms and IC manufacturing software
products to the global electronics market, enabling the development and
production of complex systems-on-chips (SoCs).

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This data is accessible by Silicon
Navigator customers through its extended API.

hossein gupta

"
The SLEC product family is the first commercially available
platform that proves functional equivalence between two IC designs
that contain differences in levels of abstraction and sequential
behavior."
The SLEC product family initially includes two products: SLEC
SYSTEM and SLEC RTL. SLEC SYSTEM is used by design teams to check that
RTL implementations match a system-level design, while SLEC RTL checks
functional equivalence between two versions of an RTL design that have
dramatically different architectures and timing.
SLEC allows designers to navigate the System-to-RTL continuum by
verifying functional equivalence across levels of sequential and data
abstraction. This gives engineers more freedom in the
design options they have, dramatically improving design efficiency. More information about
the company may be found at www. (NYSE:CDN) and available in Open Source from the Silicon
Integration Initiative (Si2).

NOTE: DesignWare, Leda, Formality, OpenVera, Vera and VCS are registered
trademarks of Synopsys, Inc.

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The SLEC sequential
equivalence checking software is based on a patent -pending hybrid
verification technology that, unlike traditional combinational
equivalence checkers , can support designs with sequential differences. With SLEC, design teams
quickly detect side effects that have been introduced during
block-level optimization. "We're pleased to be helping change the EDA
landscape by having our HDL Component Software as part of the
SiNavigator product line. Telephone:
408-200-0280. Verific's
technology has been licensed in many applications, combined shipping
more than 30,000 end-user copies., Synopsys, Inc.

provers gupta

"For design teams to realize the
advantages of system -level design they must have tools to quickly
verify that RTL implementations match system-level specifications .
Calypto will be hosting demonstrations of the SLEC product family
in booth #1818 at the 42nd annual Design Automation Conference taking
place in the Anaheim Convention Center from June 13-16 , 2005.calypto. The company is a member of the Cadence Connections
program, the IEEE-SA, the Open SystemC Initiative (OSCI), Synopsys
SystemVerilog Catalyst Program, and has an ongoing alliance with the
Model Technologies group of Mentor Graphics. The Verific system has
exceeded our expectations and saved us months of development," added
Janac.
Website: http://www.
"Synopsys was able to deliver the breadth of tools, proven methodology and
responsive support we needed to be confident in our aggressive schedule and
quality targets. "
The Synopsys Reference Verification Methodology , delivered with VCS Native
Testbench technology and the Vera tool, helps engineers to quickly implement
and deploy advanced verification environments using modern constrained-random,
coverage-driven and assertion-based verification techniques. All other trademarks or registered trademarks mentioned in this
release are the intellectual property of their respective owners.

tass technion

, LSI Product Technology Unit at Renesas Technology Corp. Likewise, RTL designers can
leverage previously validated designs to confidently make sequential
changes such as pipelining and resource sharing that would have
previously taken weeks of simulation time to verify.
SiNavigator has developed a system that extends its capability into
the language domain.com) specializes in right-first-time, leading edge,
digital Application Specific Integrated Circuits (ASIC) and system design
services.seifert@edelman.

orna naveen

----Calypto
Design Systems, Inc. SLE's proven and repeatable Think Physical(TM) design process,
tools, and semiconductor intellectual property reduce time-to-market and are
provided by one of the most experienced VLSI design teams in the industry.

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The RVM speeds
verification development by providing pre-defined base -class libraries with
advanced features for transaction modeling, transactor construction, messaging
services, verification flow, assertion checkers, and more. Discovery and Magellan are trademarks of
Synopsys, Inc.

tass abhinav

Business Editors/High-Tech Editors
Design Automation Conference 2005

SANTA CLARA, Calif.
"SLEC's ability to verify sequential differences is a strong
addition to our advanced verification methodology," said Osamu Tada,
department manager of System Level Design and Verification Technology
Dept.
Second phase of development undertaken by Silicon Navigator has
added functionality to the Verific and Open Access systems to store
unmapped and mapped RTL data. With it, SiNavigator customers can
implement front-end applications like Linting, Partitioning ,
Budgeting, Technology Mapping and Equivalence Checking among others. 95014. Corporate headquarters is located
at: 1516 Oak Street, Suite 115, Alameda, Calif.verific.

About Synopsys
Synopsys, Inc.com

Sarah Seifert
Edelman
+1-650-968-4033
sarah .

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We
developed the SLEC product family to address this critical need.com

Pricing and Availability

The SLEC product family is immediately available with support for
Verilog, VHDL, SystemC and C/C++ hardware descriptions. Pricing for
SLEC products begin at $175,000 for a one year floating license on
Linux platforms. The company delivers
software products to leading edge semiconductor and systems companies
worldwide. Telephone:
(510) 522-1555.

garg subir

Calypto Pioneers Breakthrough Verification Technology; Industry's First Sequential Equivalence Checker Enables New Generation of Functional Verification

com

Facsimile: 408-200-0281.

Silicon Logic Engineering Reduces Verification Development Time Using Synopsys' Reference Verification Methodology With VCS and Vera Solutions

"Synopsys ' RVM enables chip developers to rapidly adopt the proven
verification techniques used by the experts ," said Farhad Hayat, vice
president of Marketing, Verification Group, Synopsys, Inc.com

abhinav tass

The SLEC family delivers dramatic improvement in
integrated circuit (IC) functional verification , offering design teams
increased productivity, confidence and flexibility in making changes
to meet their IC power and performance goals. "It
offers us an innovative approach for functional verification as we
refine our design at various levels of abstraction. OpenAccess today is mostly used for layout applications. Facsimile number: (510) 522-1553. "With support in
the Vera tool and in VCS Native Testbench technology for even higher
performance, the RVM enables ASIC and system developers such as SLE to
complete their projects with a higher level of verification confidence in less
time .siliconlogic.com/ .

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SUPPORTING THE SYSTEM-TO-RTL CONTINUUM

Moving to high level design is a process of navigating the
System-to-RTL continuum.
Design teams who adopted system-level design methodologies can use
the SLEC products to leverage their investment in system-level
validation to verify and refine RTL implementations.----Silicon
Navigator Corporation, also known as SiNavigator (TM) today announced
that it has licensed HDL Component Software from Verific Design
Automation , and plans to use the license to extend the OpenAccess (OA)
database to include the ability to store , process, and analyze
Register Transfer Level (RTL) code to augment OA's existing netlist
capability .sinavigator.

lexicons spatio

94501. Email:
http://www. The collaborative relationship we have with the
Synopsys teams was also a significant factor in our decision making process. Synopsys is headquartered in
Mountain View, California and has offices in more than 60 locations throughout
North America, Europe, Japan and Asia.

gupta vlsi

Silicon Navigator corporate headquarters are located at: 10050
North Wolfe Road, Suite SW2-260, Cupertino, Calif. SLE is taking advantage of the Synopsys Reference
Verification Methodology (RVM) to reduce the development time for its
verification environment and to ensure the highest-quality verification
results.

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About Silicon Navigator

Founded in late 2003, Silicon Navigator Corporation (or
SiNavigator) is a private Electronic Design Automation (EDA) software
company whose products represent the next generation of Library
Smart(TM) tools for chip design.

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About Calypto

Founded in 2002, Calypto Design Systems, Inc. "Our
primary goal was to have a high performance front-end netlist input
for Timing Analysis and Physical Design. Having this data
available from the EMH (Embedded Module Hierarchy) of Open Access
enables new application areas.com. In addition to the VCS solution and Vera tool, SLE has adopted
Synopsys' Magellan(TM) hybrid formal analysis , Leda(R) RTL checking and
Formality(R) formal equivalency checking solutions from the Discovery(TM )
Verification Platform."
SLE (http://www.

abhinav subir

Business Editors/High-Tech Writers

CUPERTINO , Calif.
Verific's HDL Component Software -- C++ source code-based, Verilog
and VHDL parsers, analyzers and elaborators -- is now integrated with
SiNavigator's OA Framework and extend OA's capabilities to the netlist
and RTL levels.

garg abhinav

To
register for a product demonstration, please visit www."
"SiNavigator is breaking new ground in with its OpenAccess-based
framework and engines," adds Michiel Ligthart, Verific's chief
operating officer. In particular, Synopsys' RVM enables us to cut our
verification development time, while promoting industry best practices within
our verification team.

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today introduced its SLEC(TM) product family --
the semiconductor industry's only sequential logic equivalence
checking solution.calypto. George Janac, founder and CEO of Silicon Navigator, said, "We
have customers that want to use OpenAccess as a front-end database for
EDA tools. We did extensive evaluations before settling on
Verific as our partner in this endeavor."

About the Integrations

The two companies first engaged in a development to integrate the
Verific C++ system for netlists onto the OpenAccess database.com

About Verific Design Automation

Verific Design Automation was founded in 1999 by electronic design
automation (EDA) industry veteran Rob Dekker.

technion subir

A continuum approach is required for design
teams to work at multiple levels of sequential and data abstraction --
from fully-timed RTL implementation to transaction-level modeling. In both cases,
the SLEC platform delivers a comprehensive sequential verification
solution that identifies bugs that are difficult to find or missed
when using traditional simulation methods. Calypto is privately held with venture funding from Cipio
Partners, JAFCO Ventures, Tallwood Venture Capital and Walden
International.ASIC and System Developer Adopts Synopsys' Discovery(TM) Verification Platform
for 90-Nanometer Chip

MOUNTAIN VIEW, Calif. is a world leader in electronic design automation (EDA)
software for semiconductor design.

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