Customers
can efficiently run SystemC to verify system function, SystemVerilog
and Verilog
to verify gate implementation and timing, VHDL for
compatibility, PSL for complete assertion-based
verification, and AMS
for mixed-signal designs.com/partners/languages/languages.
francesco theorem
These new features
enable the
development of new, compelling, and revenue generating applications.
"With Esmertec
's complete portfolio of software solutions, we are
well positioned to offer a broad range of software
products and
platforms to satisfy diversified customers' requirements," said
Anne-Marie Larkin
, CTO. On display are over 20 new commercially available
phone models with Esmertec's Java solution
. These high-performance platform solutions
are delivered to chipset and embedded device manufacturers
.com
Esmertec and Jbed are trademarks of Esmertec AG
Java is a trademark of Sun Microsystems
, Inc.
"We've been successfully using this encryption technology with the
Incisive functional verification
platform using VHDL, and are looking
forward to seeing this capability standardized on by all hardware
description languages, including SystemVerilog," said Reno Sanchez,
director, Microprocessor Center
of Excellence, Xilinx.qian transformation
All of these languages now run inside a
single simulation interface, allowing
customers to use any combination
for design and verification to improve language interoperability
.ross parallel
"Cadence's support for SystemVerilog ensures that the
Verilog language will remain a unified industry
standard.
"Providing a single language for additional design and
verification capabilities reduces
the cost of tools and education, and
makes it easier for the new technology to be adopted.qian q
In
addition, customers are offered a broad range of platform
configurations and a comprehensive set
of Java Specification Requests
(JSRs). Our solutions are
applied in the mobile and fixed line
telecommunication,
home-multimedia, machine-to-machine, consumer electronics and
industrial automation
markets.
"Our design and verification platforms, especially the Incisive
functional verification
platform, are built around open standards that
offer customers the flexibility and language choice
needed to optimize
their verification methodology. With
approximately 4,900 employees and 2004
revenues of approximately $1.functional logic
esmertec.
At 3GSM, Esmertec is pleased to showcase its latest versions
of
Jbed Advanced and Jbed CLDC with new features including 3D Graphics,
Bluetooth, PDA-like (Enterprise
) applications, optional Jbed verifier,
key European and Asian operator extensions, as well as third
party
extensions such as IN-FUSIO's EGE.----Cadence Design
Systems, Inc.qian calculus
www.com
Cadence
, the Cadence logo and Verilog are registered trademarks of
Cadence Design Systems, Inc. Encounter
and Incisive are trademarks of
Cadence Design Systems, Inc.extensions compiler
About Esmertec
Esmertec
is a leading provider of software solutions and
technologies for mobile phones and embedded devices
.unification fault
Engineered for smallness, Esmertec's
Java (J2ME(TM)) solutions, native mobile components and platform
, and
object-oriented software (OSVM) are designed to extract maximum
performance from hardware
environments with very limited computing,
memory and energy resources.
SystemVerilog enables hardware
designers to build on the strengths
of Verilog(R) to help address the challenges in design and
verification
of next-generation system-on-chip (SoC) devices."
The adoption of the Cadence customer-proven IP
encryption
technology will allow secure distribution of IP blocks in the standard
language.unification oriented
Cadence
products and services
are used to accelerate and manage the design of semiconductors,
computer
systems, networking equipment, telecommunications equipment,
consumer electronics, and other electronics
based products. All other trademarks are the property of
their respective owners.distributed fault
"We are dedicated
to continue expanding our
product and technology offering to deliver a complete range of
innovative
high quality solutions, excellent services and further
benefits to our customers.2
billion, Cadence
has sales offices, design centers, and research
facilities around the world.ross extensions
It
will also be delivered
as a unified solution, u@phone."
Esmertec is showcasing its complete solutions portfolio on
"Chantella
" at 3GSM.q extensions
"
As the initial developer of the Verilog language, Cadence now
provides design and verification
platform support for SystemVerilog,
VHDL, Verilog, PSL/OVL, SystemC, Verilog-AMS and VHDL-AMS.aspx
About Cadence
Cadence is the world's largest supplier of electronic design
technologies
and engineering services.semantics logic
In addition, at TI's booth
B6 in Hall 1, Esmertec will be demonstrating
3D gaming with Esmertec's
Jbed, optimized to harness the power of TI's OMAP(TM) 2 architecture. These
donations enhance the data types
that are currently available in SystemVerilog and enable existing
encryption technology to be used to encrypt SystemVerilog code,
resulting in enhanced language
efficiency and usability. The company is headquartered in San Jose,
Calif.quaglia distributed
esmertec. (NYSE:CDN) (Nasdaq:CDN
) today announced that it has
donated SystemVerilog data type and intellectual property (IP)
encryption
technology to the IEEE P1800 Working Group to enhance
SystemVerilog usability. The IEEE P1800 Working
Group will incorporate
the Cadence(R) technology in the first release of the SystemVerilog
standard
, due later this year.
"Cadence has leveraged its leadership in language design and
hardware implementation
, and is providing valuable technology to
designers," said Kevin Silver, vice president marketing
for Denali
Software, Inc.
For more information, visit
http://www. More information is available
at
www.cadence.distributed q
, and trades on both the New York Stock Exchange and Nasdaq
under the symbol CDN
.francesco transformation
Cadence Donates Technology to IEEE to Enhance SystemVerilog Usability; Data Types and IP Encryption
to Be Part of Initial IEEE SystemVerilog Standard
"This
encryption technology will make it easier
for us to protect our IP as
well as help our customers gain access to a broad portfolio of
high
-value IP, and do so within an industry standards-based protocol.tolerant extensions
The solutions engineered
for the
mobile and home multimedia markets include:
Acclaimed Java runtime platforms - Jbed(TM) CLDC
, Jbed CDC,
Jbed IMP, DeltaJet and Jbed Advanced with multitasking feature
Full set
of Java applications - Email, IM, RSS, Contact
Manager, Brand Manager
Value added
mobile applications and modules - u@(TM)MMS,
u@WAP, u@SSL, Calendar, etc.
Cadence technologies
supporting SystemVerilog include the
Encounter(TM) digital IC design platform and Incisive(TM) functional
verification platform, providing customers a powerful option for
design, synthesis, formal verification
, and acceleration/emulation.semantics quinlan
Founded in
1999, Esmertec is a global company headquartered in Zurich
, with
engineering, sales and customer support operations in Switzerland,
France, Denmark, the
UK, the USA, China, Hong Kong, Korea, Japan and
Taiwan."
"In response to our customers' needs
, Cadence is driving support
for a single Verilog standard that will give users the benefits of
open
interoperability, exemplified by our recent donations to the
IEEE," said Victor Berman, director
of Language Standards at Cadence.algebraic unification
Business Editors/High-Tech Writers/Tradeshow Writers
3GSM
World Congress 2005
CANNES, France----
Featuring Its Latest Version of Jbed CLDC
and the First Commercially
Available Multitasking Java Virtual Machine - Jbed Advanced
Esmertec
(TM) (www.com), a leading provider of software
solutions for mobile phones and embedded devices, will
be
demonstrating its complete portfolio of embedded software solutions
for mobile devices at 3GSM
World Congress in Cannes.
logic proving
Esmertec Presents at 3GSM Cannes a Complete Portfolio of Embedded
Software Products for Mobile Phones and Embedded Devices
cadence.proving quaglia
Business Editors/High-Tech
Editors
SAN JOSE, Calif. The
Cadence donation provides enhanced data types that raise the
level of
abstraction in SystemVerilog, enhancing designer productivity and
language usability
.parallel logic
The technology is a major enabler for IP-based SoC design
and solves a significant industry
problem by providing a standard
mechanism for IP protection.transformation oriented
The Esmertec solutions portfolio
is grouped into three categories:
Java(TM) solutions, mobile applications and modules, and
object
-oriented software platform OSVM(TM).calculus q
These products are designed to be delivered independently and
can
be easily integrated onto a wide range of wireless handsets. This
unification is very important to
users.ross fault
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