Latest Version of the VCS(R) Solution Speeds Standards-Based Verification by
Unifying SystemVerilog and SystemC(TM) Languages in a Single Tool

MOUNTAIN VIEW, Calif. The VCS Assertion IP can be used with
designs created with SystemVerilog, Verilog, VHDL or SystemC languages.

2) Middle: types or classes of languages.

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(Nasdaq: SNPS), a world leader in semiconductor design software, today
announced the availability of the SystemVerilog source code for its
implementation of the VMM Standard Library, a base-class library to accelerate
the adoption of the SystemVerilog standard for verification.com

Sarah Seifert
Edelman
+1-650-968-4033
sarah. "Synopsys has always been committed to
delivering industry standards support in our VCS solution."

VCS Assertion IP Library for Industry-Standard Protocols
The VCS Assertion IP Library contains a set of checkers that can be used
with the VCS solution or with Synopsys' Magellan(TM) hybrid RTL formal
analysis tool to verify complex protocols within the design.1 standard. All other tradenames ,
trademarks or registered trademarks mentioned in this release are the
intellectual property of their respective owners.

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The VMM Standard
Library is specified in the ARM-Synopsys book Verification Methodology Manual
for SystemVerilog, announced by Springer Science + Business Media, Inc.idealliance .
www.com

About Lighthouse Seminars

Lighthouse Seminars' events cover information technologies and
"content technologies" in particular. First, the VCS 2005.11a-g
-- AGP
-- SMIA
-- DDR2
-- OCP 2. "Now that the VCS solution includes testbench
support for the industry -standard SystemVerilog language, we again expect to
advance our verification testbench environment for the S5000 family of
software-configurable processors.

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"Synopsys has been on the leading edge of SystemVerilog from the very
beginning, when our donations accelerated the development of the language's
verification features," said Rich Goldman, vice president, Strategic Market
Development at Synopsys. The company delivers technology-leading
semiconductor design and verification platforms and IC manufacturing software
products to the global electronics market, enabling the development and
production of complex systems-on-chips (SoCs).

NOTE: Synopsys, DesignWare, Design Compiler, Leda, OpenVera, and VCS are
registered trademarks of Synopsys, Inc. Ltd. All other trademarks or registered trademarks
mentioned in this release are the intellectual property of their respective
owners.com

Microsoft (NASDAQ: MSFT) joins Adobe Systems, Inc., Immediacy,
O'Reilly , Percussion Software, Quark, Quasar Technology, Syncro Soft,
and Vamosa. Combined with the constrained -random stimulus
generation and self-checking capabilities of DesignWare(R) Verification IP,
the VCS Assertion IP Library enables design teams to create comprehensive
block-level and chip-level verification environments that comply with
Synopsys' Reference Verification Methodology guidelines to increase design
quality and lower development cost. This powerful combination
delivers up to five times faster verification performance compared to
independent testbench and simulation environments .

Editorial Contacts:
Renae Veiga
Synopsys, Inc.

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today. + CAMBRIDGE, Mass .com/lighthouse/Amsterdam2005/gcsf.gilbane.com/.06.

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org

About Bluebill Advisors, The Gilbane Report

Bluebill Advisors, Inc. The company delivers technology-leading
semiconductor design and verification platforms and IC manufacturing software
products to the global electronics market, enabling the development and
production of complex systems-on-chips (SoCs). Actual results could differ materially from these
statements as a result of unforeseen difficulties in completing development of
the release, uncertainties attendant to any new product release and the other
factors contained in Synopsys' Quarterly Report on Form 10-Q for the fiscal
quarter ended January 31, 2004.

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Synopsys Announces Source-Code License for SystemVerilog Verification Library

Synopsys also provides
intellectual property and design services to simplify the design process and
accelerate time-to-market for its customers. At the Silver
Sponsorship level, DocSoft, Idiom and Solace Systems have been added
to a list of sponsors that includes Antenna House, Astoria Software,
AuthorIT, Exegenix, Fast Search + Transfer(TM), Inc.
"The list of sponsors and exhibitors at these events is truly a
'who's who' in XML and related technologies ," says Marion L.asp
For more information on the Gilbane Conference on Content
Management, visit
http://home.lighthouseseminars.
www.lighthouseseminars. The VCS Assertion
IP Library allows designers to perform functional checks during simulation,
identify and report protocol violations , and capture assertion coverage data.

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SystemVerilog Catalyst Program members may also license the VMM Standard
Library source code at no additional cost to facilitate compatible methodology
support for their EDA tools, verification IP and services.; ARM KK; ARM Korea Ltd.V. Learn more about IDEAlliance at www., Synopsys, Inc.

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Synopsys' VCS(R) comprehensive RTL verification solution includes the
object code for the VMM Standard Library. "This will enable a high degree of EDA
tool interoperability , particularly with the advanced capabilities of
SystemVerilog, thereby improving verification productivity and helping to
achieve first-silicon success with even the most challenging chips. "We continue that leadership by co-authoring the VMM
for SystemVerilog book with ARM and by making our implementation of the VMM
Standard Library freely available to the industry.

Synopsys Discovery Verification Platform
The Discovery(TM) Verification Platform is a unified environment that
provides high performance and efficiency of interaction among all platform
components, including mixed-HDL simulation , mixed-signal, system-level
verification, assertions, DesignWare(R) verification intellectual property ,
code coverage, functional coverage, testbenches and formal analysis. Synopsys is headquartered in
Mountain View, California and has offices in more than 60 locations throughout
North America, Europe, Japan and Asia.

Synopsys Advances VCS Solution by Adding Assertion IP Library and Native Testbench Support for SystemVerilog

06 release now adds
native support for the following SystemVerilog testbench features:

-- Automatic static task/functions
-- Clocking block
-- Dynamic and associative arrays
-- Functional coverage
-- Object-oriented programming and encapsulation
-- Program block
-- Queues
-- Random constraints
-- Threading and synchronization
-- Virtual interfaces

Built-In SystemC Language Simulator
VCS 2005.06 includes a native SystemC language simulator with support for
flexible co-simulation of mixed-HDL designs and SystemC models. Synopsys also provides
intellectual property and design services to simplify the design process and
accelerate time-to-market for its customers.
NOTE: Synopsys, VCS and DesignWare are registered trademarks of Synopsys,
Inc.

There is a vast variety of programming languages, estimates run from 2,000 to 6,000.

Yet, all languages must adhere to the central unifying principles of computer science (even Intercal and Befunge), otherwise they couldn't work.

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VCS customers may license the source
code at no additional cost to gain insight into the implementation details .org.
Included as a standard feature with the VCS 2005. Synopsys is headquartered in
Mountain View, California and has offices in more than 60 locations throughout
North America, Europe, Japan and Asia. These statements are based on Synopsys' current
expectations and beliefs.

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Combined
with support for industry-standard hardware design and verification languages,
including Verilog, VHDL , SystemVerilog, SystemC(TM) and OpenVera(R) and
Synopsys' proven Reference Verification Methodology , the Discovery
Verification Platform helps designers achieve higher levels of verification
productivity by contributing to first-time silicon success within required
project cycles.; ARM Belgium N.

CONTACT:
Renae Veiga
Synopsys, Inc.
+1-650-584-1902
renae@synopsys . (NASDAQ: ADBE)
and Blast Radius at the Gold Sponsorship level. Its mission is to advance
user -driven, cross-industry solutions for all publishing and
content-related processes by developing standards , fostering business
alliances, and identifying best practices.com

is a world leader in electronic design automation (EDA)
software for semiconductor design.seifert@edelman.

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, Synopsys , Inc. Corporate members of the
SystemVerilog Catalyst Program may gain access to Synopsys' design and
verification tools including: VCS, HDL Compiler(TM), the front-end language
compiler for Design Complier(R), and Leda(R) for the purposes of developing
SystemVerilog-based tools, ensuring their interoperability and providing
support for mutual customers.

IDEAlliance XTech 2005 Gilbane Conference Add Key Industry Sponsors for Joint Conferences in Amsterdam 24-27 May; Microsoft DocSoft Idiom Solace Software J

"Combined with the
educational and networking opportunities of the two conferences, no
one in the industry can afford to miss this unprecedented joint
event.

About Synopsys
Synopsys, Inc.

intercal multiparadigm

"Making source-code to Synopsys' implementation of the VMM Standard
Library available is a big step toward driving wide adoption of
SystemVerilog," said Michael Garcia, design and verification methodology
manager at Freescale Semiconductor.synopsys. Elledge ,
Vice President of Information Technology Alliances and Conferences,
IDEAlliance. For general information and to
register to attend, visit
http://www. These include content management
of all types, digital asset management, document management, web
content management, enterprise portals , enterprise search, web and
multi-channel publishing, electronic forms, authoring, content and
information integration, information architecture, and e-catalogs. Finally, VCS 2005.
Additionally, engineers can use the library with the Magellan tool to prove
complex design properties.

Native Testbench Technology Extended with SystemVerilog Support
The latest version of the VCS solution now supports IEEE P1800
SystemVerilog testbench features natively with its Native Testbench
technology .

obfuscated rigal

"By making their implementation of the VMM Standard Library available as
source code, Synopsys is providing a jump-start to designers to use the
verification techniques contained within the VMM for SystemVerilog," said
Tim Holden, director, EDA relations, ARM. "This will enable our Partners to
apply sophisticated SystemVerilog verification methodologies to their ARM(R)
technology-based designs and will benefit other SoC designers in the
electronics industry as a whole by offering a way of standardizing
verification.com/ . Discovery and HDL Compiler are
trademarks of Synopsys , Inc. The Gilbane
Report administers the Content Technology Works program disseminating
best practices with partners Software AG (TECdax:SOW), Sun
Microsystems (NASDAQ:SUNW), Artesia Technologies, Atomz , Astoria
Software, ClearStory Systems (OTCBB:INCC), Context Media, Convera
(NASDAQ:CNVR), IBM (NYSE:IBM), Idiom Technologies, Mark Logic, Open
Text (NASDAQ:OTEX), Trados, Vasont, and Vignette (NASDAQ:VIGN).
(Nasdaq: SNPS), a world leader in semiconductor design software, today
announced it is advancing its VCS(R) comprehensive RTL verification solution
by incorporating a number of new capabilities that enable engineers to find
more design bugs faster and achieve up to five times faster verification
performance.06 release includes the new VCS Assertion IP
Library, which includes protocol checkers for industry standards such as
AMBA(TM) 2 AHB/APB protocols and PCI(R) interfaces .
"Stretch is successfully using VCS' NTB technology to accelerate our
verification performance ," said Wayne P.com

Sarah Seifert
Edelman
650-968-4033
sarah.com

In computer science, after basic hardware, language comes first, before operating systems , applications, or anything else.

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The library enables users to adopt the advanced verification techniques and
methodology advocated in the book more quickly and easily. Visit Synopsys online at
http: //www.; AXYS GmbH; ARM Embedded Technologies Pvt."
"We couldn't be more excited about the companies participating,"
says Frank Gilbane, Gilbane Conference Chair. Second, the VCS solution
extends its customer-proven, high-performance Native Testbench (NTB)
technology to incorporate an industry -first, full-featured SystemVerilog
testbench solution.0 and
CoreConnect. Engineers using the VCS solution can now quickly create highly
effective verification environments using SystemVerilog's object-oriented,
constrained-random stimulus and functional coverage capabilities. Magellan is a trademark of Synopsys, Inc.

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"From industry giants to smaller, cutting-edge firms,
they cover the full spectrum of what's happening in XML and content
management today.xtech-conference. Heideman , vice president of
Engineering at Stretch, Inc.

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;
and ARM Physical IP, Inc.0 interface
-- AMBA 2 AHB and APB
-- 802.06 is expected to be available in the third calendar quarter of
2005 .

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VMM
Standard Library source code, which can be used with EDA tools compliant with
IEEE P1800 SystemVerilog, is planned to be available for license at no
additional charge by VCS users and SystemVerilog Catalyst members before the
end of the year. is a world leader in electronic design automation (EDA )
software for semiconductor design.html

About IDEAlliance

IDEAlliance (International Digital Enterprise Alliance) is a
not-for-profit membership organization.
"Customers are asking for proven verification technology that combines
easy-to-use assertion and verification IP with support for industry
standards," said Manoj Gandhi, senior vice president and general manager,
Verification Group, Synopsys, Inc.0. Visit Synopsys online at
http://www.

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Ltd."
For information on presentations , sponsorships, exhibiting and
other marketing opportunities at XTech 2005, visit
http://www.

Forward Looking Statements
This press release contains forward-looking statements within the meaning
of the safe harbor provisions of Section 21E of the Securities Exchange Act of
1934 , including statements regarding the expected benefits and date of
availability of VCS 2005.

The situation is often likened to the many schisms of some religions, and sometimes disagreements and even fights occur among the faithful.

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About Synopsys
Synopsys, Inc. IDEAlliance builds on
these languages to create specifications that enhance efficiency and
speed information in all aspects of publishing and content-related
processes. The latest release
now combines our proven, Native Testbench and assertion-based verification
technology with SystemVerilog and SystemC languages to deliver higher
verification throughput with the flexibility provided by open standards.synopsys.

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SystemVerilog
Catalyst Program members can provide compiled, object-code versions of the
library to their customers.

About the SystemVerilog Catalyst Program
Synopsys' SystemVerilog Catalyst Program promotes the development and use
of EDA tools, verification IP and training services supporting the
SystemVerilog standard for design and verification. ARM is a registered trademark of ARM Limited.;
AXYS Design Automation Inc.org/2005/registration. Founded in 1966 as the
Graphic Communications Association, IDEAlliance has been a leader in
information technology - developing Document Markup Metalanguage
(GENCODE), sponsoring the Standard Generalized Markup Language (SGML),
and fostering eXtensible Markup Language (XML). VCS' NTB
technology deploys a unique, single-compiler architecture to simultaneously
optimize design, testbench, assertions and coverage."
In addition to support for SystemVerilog design constructs, assertions and
the Direct Programming Interface (DPI), the VCS 2005.

On this page, languages are arranged in three groups and levels: 1) Top: issues spanning multiple unrelated languages.

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Availability
VMM Standard Library object code is available today for VCS users.
"ARM" is used to represent ARM Holdings plc; its operating company ARM
Limited; and the regional subsidiaries ARM INC.xtech-conference.

Availability
VCS 2005.

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Business Editors/High-Tech Editors
XTech 2005 Conference
Gilbane Conference on Content Management Technologies 2005

ALEXANDRIA, Va.----XTech 2005 (formerly XML Europe) and the Gilbane Conference on
Content Management today announced four new industry sponsors for
their conferences, being held concurrently 24-27 May, 2005, at the
Amsterdam RAI Centre, Amsterdam, Netherlands.06 delivers native SystemC language
simulation.06 release, the VCS
Assertion IP is provided for the following interface and protocol standards:

-- PCI and PCI-X(R) 2.

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VMM Standard Library Enables Adoption of Techniques in the ARM-Synopsys
Verification Methodology Manual (VMM) for SystemVerilog

MOUNTAIN VIEW, Calif. Synopsys' implementation of the VMM Standard
Library is based on IEEE P1800 SystemVerilog for easy tool interoperability,
and has been extensively tested with the VCS solution.; ARM
Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co. serves the content management community
with publications , conferences and consulting services.

One needs a language first, even if only machine language, before one can write any software at all.

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seifert@edelman. Justsystem Corporation is the Diamond Sponsor of both
events.0
-- LPC

Additional protocol standards are planned to be supported in future
releases of the VCS solution, including PCI Express(TM) interface, USB 2. The VCS native
SystemC language simulation capability is compliant with the OSCI SystemC
language 2.
650-584-1902
renae@synopsys.

3) Bottom: specific languages, with their own directory category .

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