PureTime, a software timing exception verifier, extends Real Intent 's
formal technology to address design implementation challenges early in the
design cycle.

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Jasper Design Automation Enables 100% Actual Coverage for VHDL Users

com.

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VHDL is
the predominant design language used in Europe, where Jasper is
exhibiting for the first time at the Design and Test Conference (DATE)
this week in Munich, Germany.com

Jasper Design Automation, the Jasper Design Automation logo,
JasperGold, PreCognitive Engine, Design Tunneling and Jasper Formal
Testplanner are trademarks of Jasper Design Automation, Inc.

WHAT:

The new Verix Convergence Engine improves the capacity and performance of
the entire Verix product family
-- Implied Intent Verification, Expressed Intent Verification and
Clock Intent Verification software -- so that many designs which were
impossible to formally verify, can now be verified.

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PRESS RELEASE Reminder - Real Intent Invites Electronic Design +amp; Verification Community to Demos of Formal Verification From Spec to Sign-off at DVCon

WHEN:

Exhibit and Verix demonstrations:

Wednesday, February 22,4:00 pm - 7:00 pm, and Thursday, February 23, 4:00
pm - 7:00 pm

WHERE:

DoubleTree Hotel San Jose
2050 Gateway Place
San Jose, CA 95110
Phone: 408-453-4000
Booth # 404

Information and Registration:

Please visit www.

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Real
Intent's products dramatically improve the functional verification
efficiency of leading edge application-specific integrated circuit (ASIC),
system-on-chip (SOC ), and Field Programmable Gate Array (FPGA) devices.

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It can prove the correctness of timing exceptions created by
designers, or in existing Intellectual Property (IP), using exhaustive
analysis and help avoid timing exception errors that create schedule
delays, chip re-spins or failing hardware .





DVCon


About Real Intent:

Real Intent is extending breakthrough formal technology to critical
problems encountered by design and verification teams worldwide.

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com for more information.

Founded in 1999, Real Intent is a privately held Electronic Design
Automation (EDA) company headquartered at 505 North Mathilda Avenue, Suite
210, Sunnyvale, CA 94085, phone: (408) 830-0700 fax: (408) 737-1962, web:
info@realintent .

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dvcon.

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To register for demonstrations or schedule a meeting with Real Intent
please visit www .

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Business Editors/High-Tech Editors
Design, Automation and Test in Europe (DATE)

MUNICH , Germany----

JasperGold Breakthrough Formal Verification Solution
Now Supports VHDL Verification and Debugging

Jasper Design Automation, provider of breakthrough high -level
formal verification solutions, today announced that its flagship
product, JasperGold(TM ), now supports verification and debugging of
designs written in the VHDL language, in addition to Verilog. "With
support for VHDL, and a very disciplined verification methodology for
achieving 100% coverage of blocks as they are being designed,
JasperGold is sure to capture the attention of Europe's leading design
teams, renowned for their rigorous design quality.

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"

Availability

VHDL language support is available today within JasperGold v3.

Over 30 major electronics design houses, including Sun Microsystems, ATI,
Avago Technologies, nVidia, and NEC Electronics, use Real Intent software. All other trademarks and tradenames are the property of their
respective owners.

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For further
details on how to improve design quality, verification productivity,
predictability and verification reuse, visit http://www.


WHO:

Real Intent, the leader in formal verification from spec to sign-off,
offers 2006 Design and Verification Conference (DVCon) attendees the
opportunity to see demonstrations of its PureTime and Verix
software.

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With 10x the capacity
of other formal solutions, JasperGold is unique in its ability to
fully prove high-level requirements on designer -sized blocks, ensuring
that the most important aspects of a design, derived from the design
specification , are verified with 100% actual coverage. All other
names mentioned are trademarks, registered trademarks , or service
marks of their respective companies.

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1,
at no additional charge to licensees of JasperGold .

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About Jasper Design Automation

Founded in 1999, Jasper Design Automation is a privately -held
Electronic Design Automation (EDA) company headquartered in Mountain
View, California.

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jasper -da.

Verix, Convergence Engine, Implied Intent Verification, Expressed Intent
Verification and Clock Intent Verification are trademarks of Real Intent
Inc.

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"Having been used successfully in verification and debug of more
than 45 production chips written in Verilog, JasperGold is already
changing the way designers think about verification in North America
and Japan," said Kathryn Kranen, president and CEO at Jasper. The first verification product to deliver 100%
actual coverage within predictable, finite schedule constraints, the
JasperGold(TM) solution formally verifies that complex design blocks
meet their high-level requirements, as defined by their
specifications, without any testbench development.realintent.com.

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Application areas include linguistics and computer science, in particular program verification.

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By providing verification and debugging
support for VHDL, Jasper now enables VHDL users worldwide to break
through the coverage barrier and achieve 100% actual coverage in the
verification of even their most complex digital designs .
JasperGold is the first formal verification solution to deliver
100% actual coverage on a complete set of high-level requirements,
predictably and within verification schedule constraints. High-level
requirements are similar to assertions and are compatible with
assertion-based verification (ABV ), but they work at a higher level of
abstraction, enabling greater design coverage and higher proof of
correctness, independent of the implementation. JasperGold
automatically isolates bugs with a fast, unique debugging capability,
trimming crucial months off the verification schedule.

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