SLE is taking advantage of the Synopsys Reference
Verification Methodology (RVM) to reduce the development time for its
verification environment and to ensure the highest-quality verification
results.com) specializes in right-first-time, leading edge,
digital Application Specific Integrated Circuits (ASIC) and system design
services. Discovery and Magellan are trademarks of
Synopsys, Inc.

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Bluespec is a trademark of Bluespec,
Inc. All other trademarks or registered trademarks mentioned in this
release are the intellectual property of their respective owners.com

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More information can be found on
www. Combined with support
for industry-standard hardware design and verification languages, including
Verilog, VHDL, SystemVerilog, SystemC(TM) and OpenVera(R) and Synopsys' proven
Reference Verification Methodology, the Discovery Verification Platform helps
designers achieve higher levels of verification productivity by contributing
to first-time silicon success within required project cycles.

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"
The Synopsys Reference Verification Methodology, delivered with VCS Native
Testbench technology and the Vera tool, helps engineers to quickly implement
and deploy advanced verification environments using modern constrained-random,
coverage-driven and assertion-based verification techniques.siliconlogic . Synopsys also provides
intellectual property and design services to simplify the design process and
accelerate time-to-market for its customers.

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com/ .

synthesizable proprietary

----Bluespec Inc.,
www.

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, Synopsys, Inc .

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Visit Synopsys online at
http://www.

transformational primer

"Synopsys was able to deliver the breadth of tools, proven methodology and
responsive support we needed to be confident in our aggressive schedule and
quality targets.

CONTACT:
Isela Warner
Synopsys, Inc.seifert@edelman .

hardware transformational

Availability

Bluespec's cosimulation support is available now.
(Nasdaq: SNPS), a world leader in semiconductor design software, today
announced that Silicon Logic Engineering (SLE), a provider of high-end ASIC
and system design services, has adopted Synopsys' VCS (R) comprehensive RTL
verification solution and Vera(R) testbench automation tool to accelerate its
chip development process.
"We chose Synopsys as our verification partner on our latest 90-nanometer,
40-million -gate chip development project after evaluating several providers,"
said Bob Solberg, vice president of Operations and co-founder at SLE. SLE's proven and repeatable Think Physical(TM) design process,
tools, and semiconductor intellectual property reduce time-to-market and are
provided by one of the most experienced VLSI design teams in the industry.

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"Bluespec gives you
fast, cycle-accurate models that can be co-simulated in your existing
environment.

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com, developer of the only behavioral synthesis solution
for control logic and complex datapaths, announced today it has added
cosimulation capabilities to its model simulation technology that will
allow hardware chip designers to utilize Bluespec's cycle-accurate
models in SystemC or Verilog modeling environments.

About Bluespec

Bluespec Inc.

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The cosimulation capabilities enable a heterogeneous design
component environment to be easily simulated. Bluespec will automatically
generate all of the shims required for these models to co-simulate.
"Synopsys' RVM enables chip developers to rapidly adopt the proven
verification techniques used by the experts," said Farhad Hayat, vice
president of Marketing, Verification Group , Synopsys, Inc.

About Synopsys
Synopsys, Inc. is a world leader in electronic design automation (EDA)
software for semiconductor design.

abstraction methodology

"From modeling to RTL, Bluespec is bridging specifications,
modeling and implementations to deliver a comprehensive ESL
capability," said George Harper, VP Marketing. The collaborative relationship we have with the
Synopsys teams was also a significant factor in our decision making process.

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ASIC and System Developer Adopts Synopsys' Discovery (TM) Verification Platform
for 90-Nanometer Chip

MOUNTAIN VIEW , Calif. In addition to the VCS solution and Vera tool, SLE has adopted
Synopsys' Magellan(TM) hybrid formal analysis, Leda(R) RTL checking and
Formality(R) formal equivalency checking solutions from the Discovery(TM)
Verification Platform.

NOTE: DesignWare, Leda, Formality, OpenVera , Vera and VCS are registered
trademarks of Synopsys, Inc.

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abel knowhow

bluespec. manufactures an industry standards -based Electronic
Design Automation (EDA) toolset that significantly raises the level of
abstraction for hardware design while retaining the ability to
automatically synthesize high quality RTL, without compromising speed,
power or area. In addition,
Synopsys provides extensive RVM documentation and offers training to enable
both small and large chip development teams to quickly implement industry best
practices for verification. The company delivers technology-leading
semiconductor design and verification platforms and IC manufacturing software
products to the global electronics market , enabling the development and
production of complex systems-on-chips (SoCs).

architectures hardware

This provides
design engineers with the flexibility to leverage accelerated models
in the most appropriate and preferred environment for a given stage in
design. With growing use of IP,
it is essential that designers mix high-level design with existing IP
blocks, at any level of abstraction.com

Copyright 2005 Bluespec, Inc. All other brands, products, or service names may be trademarks or
service marks of the companies with which they are associated.

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Bluespec Adds Cosimulation to Its Cycle-Accurate Models; Supports Both SystemC and Verilog Environments Providing Engineers with Flexibility while Retaining S

Synopsys is headquartered in
Mountain View, California and has offices in more than 60 locations throughout
North America, Europe, Japan and Asia.com

Sarah Seifert
Edelman
+1-650-968-4033
sarah.

abstraction meta

These cycle-accurate models not only help debug, but can
be delivered to the system-level customer to accelerate software
development or design-in. The RVM speeds
verification development by providing pre-defined base-class libraries with
advanced features for transaction modeling, transactor construction, messaging
services, verification flow, assertion checkers, and more."
SLE (http://www.

Synopsys Discovery Verification Platform
The Discovery Verification Platform is a unified environment that provides
high performance and efficiency of interaction among all platform components,
including mixed-HDL simulation, mixed-signal, system-level verification ,
assertions, DesignWare(R) verification intellectual property, code coverage,
functional coverage , testbenches and formal analysis.

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Business Editors/Technology Editors

WALTHAM, Mass. The cycle-accurate models can be
integrated into a Verilog System-on-a-Chip (SOC) design,
back-annotated into a SystemC model or testbench or become part of a
mixed SystemC/Bluespec model.bluespec.

Silicon Logic Engineering Reduces Verification Development Time Using Synopsys' Reference Verification Methodology With VCS and Vera Solutions

systemc hardware

"
Bluespec's EDA toolset generates Verilog RTL and cycle-accurate
executables from a high-level design. The toolset, the only one focused on control and
complex datapaths, allows ASIC and FPGA designers to significantly
reduce design time, bugs and re-spins that contribute to product
delays and escalating costs. In particular, Synopsys' RVM enables us to cut our
verification development time, while promoting industry best practices within
our verification team.synopsys.
+1-650-584-1644
igamboa@synopsys.

notation hdls

"With support in
the Vera tool and in VCS Native Testbench technology for even higher
performance, the RVM enables ASIC and system developers such as SLE to
complete their projects with a higher level of verification confidence in less
time .

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